1. Technical Field
The present disclosure relates to semiconductor devices and more particularly to, a semiconductor flash memory device and method of fabricating the same.
2. Discussion of the Related Art
Semiconductor memory devices can be either volatile or nonvolatile. Volatile semiconductor memory devices lose data stored in memory cells when there is no external power supply. Examples of volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM). Nonvolatile semiconductor memory devices retain their data stored in memory cells even without external power supply. Examples of nonvolatile memory devices include flash memory devices.
Flash memory devices have floating gate electrodes for storing charges and control gate electrodes for discharging or injecting charges from or into the floating gate electrodes. Flash memory devices may be classified into split-gate and stack-gate types.
FIG. 1 is a sectional view illustrating a general split-gate type semiconductor flash memory device.
As shown in FIG. 1, a source region 32s is provided in a predetermined portion of a semiconductor substrate 10 and a pair of floating gate electrodes 24 are provided over the semiconductor substrate 10 adjacent to both sides of the source region 32s. Between the floating gate electrodes 24 and the semiconductor substrate 10 are interposed gate insulation films 22. Field oxide films 18 are laid on the floating gate electrodes 24. As the field oxide films 18 are formed on the floating gate electrode 24, the top edges of the floating gate electrode 24 are shaped in a tip. The reverse sides of the floating gate electrodes 24 to the source region 32s partially overlap with inter-gate insulation films 26 and control gate electrodes 28. The control gate electrodes 28 extend from the floating gate electrodes 24 to predetermined portions that are spaced from the source region 32s in the semiconductor substrate 10. Drain regions 32d are disposed in the semiconductor substrate 10 adjacent to the control gate electrodes 28.
The split-gate type flash memory device is structured such that the floating gate electrode 24 partially overlaps with the control gate electrode 28. The floating gate electrode 24 is completely isolated without any external electrical connection thereto. Data can be stored into the memory cell in the mechanism of current variation through the memory cell by injecting (writing) or discharging (erasing) electrons into or from the floating gate electrode 24.
Injecting electrons into the floating gate electrode 24 is accomplished by applying a high voltage, for example over 15V, and appropriate voltages to the source region 32s and the control gate electrode 28, respectively. Thereby, hot electrons are injected into the floating gate electrode 24 through the gate insulation film 22 from the semiconductor substrate 10 under the floating gate electrode 24. During this, the gate insulation film 22 couples the floating gate electrode 24 with the voltage applied to the source region 32s, boosting a voltage at the floating gate electrode 24.
Discharging electrons from the floating gate electrode 24 is accomplished by applying a high voltage, for example over 15V, to the control gate electrode 28. Thereby, a strong electric field is set on the tip-shaped top edge of the floating gate electrode 24, releasing electrons from the floating gate electrode 24 into the control gate electrode 28. During this, the inter-gate insulation film 26 acts to reduce a coupling ratio between the floating and control gate electrodes 24 and 28, maintaining a large potential gap therebetween.
As such, injecting electrons into the floating gate electrode 24 can be accomplished by channel hot electron injection (CHEI), while discharging electrons from the floating gate electrode 24 can be accomplished by Fowler-Nordheim (F-N) tunneling through the inter-gate insulation film 26 between the floating and control gate electrodes 24 and 28.
As discussed above, the split-gate type flash memory device is structured such that the floating gate electrode partially overlaps with the control gate electrode. When there is miss-alignment during a photolithography process for patterning the control gate electrode, effective lengths of channels through which the control gate electrodes overlap with the semiconductor substrate may be irregular. Operational characteristics may then be non-uniform between memory cells. For example, odd and even-numbered memory cells forming a pair which are arranged symmetrically in a mirror type may not be uniform.
Moreover, as the size of flash memory devices is reduced and integration density of semiconductor apparatuses increases, an effective channel length through which the control gate electrode overlaps with the semiconductor substrate becomes shorter and disturbance characteristics therein degrade.
Additionally, a length of the floating gate electrode becomes shorter, short channel effect may result, degrading the efficiency of operation in the flash memory device.